Dynamic random access memories (DRAMs) provide tremendous benefits in terms of storage density and are capable of transferring large amounts of data very quickly if that data is carefully organized into long bursts of consecutive data transfers to and from adjacent memory locations. Since the data interfaces of these DRAMs are limited in their per-pin bandwidth, high bandwidths are achieved through very wide data interfaces.
Certain applications, such as network communications involve the storage and retrieval of relatively small units of data, for example 64 bytes, at bandwidths which exceed 40 Gigabits per second. Wide data interfaces make it impractical to achieve data bursts long enough to make the gaps between bursts insignificant. DRAM access cycles require that a particular row within the device be selected for access and then “precharged.” Within a row, column locations can be accessed for reads or writes in rapid sequence. Hence, short random accesses suffer from the precharge latency overhead on each cycle thereby significantly reducing the available bandwidth.
DRAMs can feature multiple independent banks which allow for the overlapping, or pipelining, of memory accesses. DRAMs which implement multiple banks can precharge each of the banks independently. For a read or write access to a bank, that bank is pre-charged independently of other banks. This allows the system designer to “hide” the precharge behind other precharge or data transfer operations. Hence, the presence of multiple banks can reduce precharge latency and increase the utilization of the DRAM's data bus.
However, if a sequence of DRAM accesses were all addressed to the same bank, the benefits of hiding the access latencies behind multiple, overlapping bank operations is lost. It is desirable that a sequence of random DRAM accesses not be targeted at the same banks in order to reduce the precharge latency.